1. Field of the Invention
The present invention relates to a method of capacity acquisition of a semiconductor device and in particular relates to a method of capacity measurement of an SOI device that is not provided with a body contact. The present invention also relates to a TEG system for capacity measurement.
2. Description of the Related Art
In an SOI device, a semiconductor substrate layer and a transistor-forming layer formed thereon are insulated and isolated by a buried oxide film. Consequently, insulation and isolation between the adjacent elements can easily be achieved and the phenomenon of “latching up” can be prevented, since no parasitic thyristors are formed through the semiconductor substrate layer. Also, creating the transistors in the SOI layer is effective in suppressing the so-called short channel effect, in which the power consumption increases as the transistor is downsized. Since the junction capacity of the transistors formed in the SOI structure is smaller than in the case of transistors of bulk structure, high-speed operation can be achieved in the SOI structure. Thus transistors formed in the SOI structure have many excellent properties. In particular, higher speed operation and lower power consumption can be achieved in the SOI structure than in the case of semiconductor elements formed in a conventional bulk substrate.
Depending on the thickness of the semiconductor-forming layer (SOI layer), SOI devices may be classified into partially depleted SOIs (PD SOIs) and fully depleted SOIs (FD SOIs). An ordinary bulk structure CMOS process can be directly used in PD SOIs, and therefore PD SOIs can be manufactured less costly than FD SOIs. However, since PD SOIs have a thick(er) SOI layer (transistor forming layer), more hole accumulation takes place in the area directly above the insulating layer (channel underlayer area), due to the so-called impact ionization phenomenon. This results in a problem that a kink effect occurs in the current/voltage characteristic of the transistors. In order to solve this problem, a body contact region is provided in the transistor-forming layer in the case of PD SOIs. The body contact region fixes the body potential so that holes accumulated in the body region are removed. In contrast, in the case of an FD SOI, the SOI layer is much thinner, with the result that the kink effect does not occur. Therefore, normally a body contact region is not provided, and the body potential is floating.
A TEG (test element group) system is sometimes employed in order to ascertain the basic properties of a SOI device. An assessment of whether or not the device manufacturing process has been performed satisfactorily is made by evaluating for example the electrical properties and reliability of the transistors by using such a TEG. When LSI design engineers verify for example variations in LSI properties resulting from tolerances given to the structural elements, the type of circuit and the design values of constants, the engineers use computer simulation. The operation and properties of the circuit may be predicted using a computer, in order to control for example the performance and operational stability of the finished product. In this way, a reduction in the number of times trial manufacture is carried out and/or reduction in the amount of work involved can be achieved. When executing circuit simulation with a computer (simulator), the parameters of the elements constituting the circuit must be entered to the simulator. For a semiconductor device prepared by a new manufacturing process, parameters that are to be entered to the simulator are unknown. In this case, the necessary parameters are acquired from actual measurement data obtained using a TEG. Appropriate simulation results for the device are obtained by inputting to the simulator the parameters obtained based on the actual measurement.
Japanese Patent Application Kokai (Laid-Open) No. 2004-253564 discloses a method for measuring the capacity of parasitic transistors of a SOI device by using three TEGs with different electrode widths.
In the case of the PD SOI, the capacitance between the body and source or between the body and drain of a SOI transistor can easily be measured by probing between the source (drain) electrode and the body contact electrode. However, in the case of a device in which no body contact is provided (hereinbelow referred to as a “body floating type”), such as an FD SOI, direct measurement of the capacity is not possible.
In the case of a SOI device having a body contact, the gate electrode in the vicinity of the body contact is a so-called H-shaped or T-shaped gate. This gate electrode is larger than a gate electrode of a body floating type device. The capacity between the body and source (drain) of a device having a body contact is therefore larger than that of a device of the body floating type. Specifically, the capacity between the body and source (drain) is a combination of the junction capacity and gate capacity between the body and source (drain). Thus, it is affected by the gate electrode area. Consequently, the capacitance between the body and source (drain) measured in a device having a body contact cannot be applied directly to a body floating type device. If this value is nevertheless applied in the circuit simulation, the simulation results such as for example delay time diverge from actual measurements and circuit design etc cannot be accurately performed.